A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor that can be widely used in digital circuits and analog circuits.
FIG. 8 is a cross-sectional schematic diagram that shows a conventional metal-oxide-semiconductor field-effect transistor (MOSFET). As shown in FIG. 8, the MOSFET comprises: a substrate 100, a source/drain region 110, a source/drain extension region 111, a dummy gate stack and a spacer 240. The dummy gate stack is formed on the substrate 100, and comprises a gate dielectric layer 210, a dummy gate 220 and a cap layer 230. The source/drain region 110, formed in the substrate 100, is positioned at both sides of the dummy gate stack. The source/drain extension region 111 extends from the source/drain region 110 to beneath the dummy gate stack, with a thickness less than that of the source/drain region 110. The spacer 240 is positioned on the sidewall of the dummy gate stack and covers the source/drain extension region 111. A contact layer 112 is provided on the source/drain region 110 (which is beneficial to the reduction of contact resistance) for forming a metal silicide layer with respect to the Si-containing substrate. In the following, the description is made by taking the Si-containing substrate as an example, the contact layer being referred as the metal silicide layer.
Although the contact resistance between the source/drain region and the metal silicide layer can be reduced in the above method, the method is only limited to forming the metal silicide layer on the source/drain region, rather than forming the metal silicide layer on the source/drain extension region below the spacer, thereby being impossible to further reduce the contact resistance between the source/drain extension region and the metal silicide layer so as to improve the performance of the MOSFET. In addition, in the replacement gate process, it is necessary to remove the dummy gate stack after forming the metal silicide layer 112 and an interlayer dielectric layer for covering the source/drain region 110, and then form the gate dielectric layer of MOSFET formed by a high K dielectric material, so as to effectively reduce the leakage current of the gate. However, when the high K gate dielectric layer is formed, the molecular structure of the high K gate dielectric layer may have small defects. In order to repair the defect, it is necessary to perform annealing to the high K gate dielectric layer at a relatively high temperature (600° C.-800° C.). However, the metal or alloy used in the metal silicide layer in MOSFET cannot withstand the high temperature necessary for annealing the high K dielectric layer, and its structure will be changed at a high temperature, thereby increasing the resistivity of the metal silicide and thus degrading the performance of the transistor.
Therefore, it is a problem urgently to be solved to effectively reduce the contact resistance in the semiconductor structure while maintaining good performance of the semiconductor structure in the subsequent high temperature process.